Data Sheet

ADL6012

Rev. 0 | Page 19 of 24

THEORY OF OPERATION

The ADL6012 uses Schottky diodes in a two path detector

topology. One path responds during the positive half cycles of

the input, and the other responds during the negative half

cycles of the input, achieving full wave signal detection. This

arrangement presents a constant input impedance throughout

the full RF cycle, preventing the reflection of even order harmonic

distortion components back toward the source. This reflection

is a well known phenomenon of widely used, traditional, single-

Schottky diode detectors. Detector response time at lower RF

frequencies is also improved with symmetrical detection.

The diodes are arranged on the chip to minimize the effect of

chip stresses and temperature variations. The diodes are biased

by small, keep alive currents chosen in a trade-off between the

inherently low sensitivity of a diode detector and the need to

preserve envelope bandwidth. Therefore, the corner frequency

of the front-end, low-pass filtering is a weak function of the

input level. At low input levels, the −3 dB corner frequency is at

approximately 2 GHz.

DC voltages at the RFIN pin (Pin 3) are blocked by an on-chip

capacitor. The two RFCM ground pins, Pin 2 and Pin 4, on

either side of RFIN form part of an RF coplanar waveguide

(CPWG) launch into the detector. The RFCM pins must be

connected to the signal ground. Give careful attention to the

design of the PCB in this area.

The output stage impedance is 100 Ω differential with propagation

delay under 1 ns, and an envelope bandwidth over 500 MHz.

The differential outputs, VENV+ and VENV− (Pin 8 and Pin 9,

respectively) provide the high speed envelope information for

both the positive and negative cycles of the RF input signal.

BASIC CONNECTIONS

The basic connections are shown in Figure 59. A dc supply of

nominally 3.3 V to 5 V is required. The bypass capacitors (C2

and C3) provide supply decoupling for the device. Place these

capacitors as close as possible to VPOS (Pin 5). The exposed

pad is internally connected to the IC ground and must be soldered

down to a low impedance ground on the PCB. OCOM (Pin 6)

is the output common. Connect OCOM to a low impedance

ground plane together with the exposed pad. DCPL (Pin 10) is

connected to an internal bias node. Place a 0.1 µF capacitor to

ground for the best common-mode noise rejection.

RFIN

ENBL

RFCM

RFIN

EPAD

DCPL

VENV+

VENV–

VENV+

VENV–

0.1µF

0.1µF

1

2

10

9

8

ADL6012

3

RFCM

VPOS

VOCM

OCOM

4

7

6

5

C3

100pF

C2

1µF

C1

0.1µF

+5V

+5V

Figure 59. Basic Connections

RF INPUT

The RFIN single-ended input is internally terminated and

internally ac-coupled. No external matching is required up to

67 GHz. The simplified input stage is shown in Figure 60. The

input trace can be directly routed with CPWG with ground on

both sides of the signal trace shown in Figure 65 and Figure 66.

Broadband response is achieved with small vias on both sides of

the signal trace and microwave dielectric material. The trace

width, gap, and dielectric thickness for the CPWG is designed

to the characteristic impedance of 50 Ω to ensure the

broadband matching is achieved for the best frequency flatness.

The RFCM pins are the ground return to the RF input. It is

critical that these pins are connected to the low impedance

ground plane, and serve as ground for the CPWG.

RFCM

RFIN

200Ω

ENVELOPE

–

+

200Ω

RFCM

Figure 60. Input Stage