 2018 Microchip Technology Inc.

DS20005447A-page 1

LP0701

Features

• Ultra-Low Threshold

• High Input Impedance

• Low Input Capacitance

• Fast Switching Speeds

• Low On-Resistance

• Freedom from Secondary Breakdown

• Low Input and Output Leakage

Applications

• Logic-Level Interfaces

• Solid-State Relays

• Battery-Operated Systems

• Photovoltaic Drives

• Analog Switches

• General Purpose Line Drivers

General Description

The

LP0701

Enhancement-mode

(normally-off)

transistor uses a lateral MOS structure and a

well-proven silicon-gate manufacturing process. This

combination produces a device with the power

handling capabilities of bipolar transistors and the high

input impedance and positive temperature coefficient

inherent in MOS devices. Characteristic of all MOS

structures, this device is free from thermal runaway and

thermally induced secondary breakdown.

The low threshold voltage and low on-resistance

characteristics are ideally suited for handheld and

battery-operated applications.

Package Type

See Table 3-1 and Table 3-2 for pin information.

3-lead TO-92

(Top view)

GATE

SOURCE

DRAIN

8-lead SOIC

(Top view)

D

D

D

D

G

S

NC

NC

s

P-Channel Enhancement-Mode Lateral MOSFET