MPF5023AMBA0ES datasheet(53/91 Pages) NXP

53 / 91 page

NXP Semiconductors

PF5023

Power management integrated circuit (PMIC) for high performance applications

PF5023

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Product data sheet

Rev. 1 — 15 April 2020

53 / 91

Table 48. OV debounce timer configuration

OV_DB[1:0]

OV debounce time

30 µs

50 µs

80 µs

125 µs

The default value of the OV_DB[1:0] upon a full register reset is 0b00.

The VMON_EN bits enable or disable the OV/UV monitor for each one of the external

regulators (SWxVMON_EN).

• When the VMON_EN bit of a specific regulator is 1, the voltage monitor for that specific

regulator is enabled.

• When the VMON_EN bit of a specific regulator is 0, the voltage monitor for that specific

regulator is disabled.

By default, the VMON_EN bits are set to 1 on power up.

When the I2C_SECURE_EN = 1, a secure write must be performed to set or clear the

VMON_EN bits to enable or disable the voltage monitoring for a specific regulator.

On enabling a regulator, the UV/OV monitor is masked until the corresponding regulator

reaches the point of regulation. If a voltage monitor is disabled, the UV_S and OV_S

indicators from that monitor are reset to 0.

Figure 24 shows the PF5023 voltage monitoring architecture.

MPF5023AMBA0ES 数据表(PDF) 53 Page - NXP Semiconductors