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ADL9006ACGZN-R7 数据表(PDF) 12 Page - Analog Devices |
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ADL9006ACGZN-R7 数据表(HTML) 12 Page - Analog Devices |
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12 / 14 page ![]() ADL9006 Data Sheet Rev. 0 | Page 12 of 14 THEORY OF OPERATION The ADL9006 is a GaAs, pHEMT, MMIC low noise amplifier. The basic architecture of the ADL9006 is that of a single-supply, biased, cascode distributed amplifier with an integrated RF choke for the drain. A simplified schematic of this architecture is shown in Figure 37. RFIN VGG2 VDD RFOUT TRANSMISSION LINE TRANSMISSION LINE Figure 37. Architecture and Simplified Schematic Though the gate bias voltages of the upper field effect transistors (FETs) are set internally by a resistive voltage divider tapped off of VDD, the VGG2 pin is provided to allow the user an optional means of changing the gate bias of the upper FETs. Adjustment of the VGG2 pin voltage across the range of −2.0 V to +2.6 V changes the gate bias of the upper FETs, thus affecting gain changes, depending on the frequency (see Figure 17). |
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