ADRF5043

Data Sheet

Rev. 0 | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V1

EN

GND

RFC

VSS

GND

GND

GND

GND

RF2

RF3

GND

1

2

3

4

5

6

LS

7

8

9

10

11

12

13

14

15

16

17

18

GND

19

20

21

22

23

24

TOP VIEW

(Not to Scale)

ADRF5043

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED TO THE RF AND DC GROUND.

Figure 3. Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN

Enable Input. See Table 6 for the truth table. See Figure 5 for the interface schematic.

2

V1

Control Input 1. See Table 6 for the truth table. See Figure 5 for the interface schematic.

3, 5, 9, 11 to 13, 15 to

17, 19 to 21, 23

GND

Ground. The GND pins must be connected to the RF and dc ground of the PCB.

4

RFC

RF Common Port. RFC is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required

when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.

6

VSS

Negative Supply Voltage.

7

LS

Logic Select Input. See Table 6 for the truth table. See Figure 5 for the interface schematic.

8

VDD

Positive Supply Voltage.

10

RF4

RF Throw Port 4. RF4 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required

when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.

14

RF3

RF Throw Port 3. RF3 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required

when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.

18

RF2

RF Throw Port 2. RF2 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required

when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.

22

RF1

RF Throw Port 1. RF1 is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is required

when the RF line potential is equal to 0 V dc.

24

V2

Control Input 2. See Table 6 for the truth table. See Figure 5 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground.

INTERFACE SCHEMATICS

RFC,

RF1,

RF2,

RF3,

RF4

Figure 4. RFC and RF1 to RF4 Pin Interface Schematic

V1, V2, EN, LS

Figure 5. V1, V2, EN, and LS Pin Interface Schematic