ADSP-21486KSWZ-2AB datasheet(44/71 Pages) AD

44 / 71 page

Rev. H

Page 44 of 71

February 2020

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Sample Rate Converter—Serial Output Port

For the serial output port, the frame sync is an input, and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output has a hold time and delay

specification with regard to serial clock. Note that serial clock

rising edge is the sampling edge, and the falling edge is the

drive edge.

Table 41. ASRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

tSRCCLKW

Clock Width

(tPCLK × 4) ÷ 2 – 1

tSRCCLK

Clock Period

tPCLK × 4

Switching Characteristics

tSRCTDD

Transmit Data Delay After Serial Clock Falling Edge

9.9

tSRCTDH

Transmit Data Hold After Serial Clock Falling Edge

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

Figure 27. ASRC Serial Output Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCTDD

tSRCTDH

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