MAS3519F datasheet(9/92 Pages) MICRONAS

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DATA SHEET

MAS 35x9F

Micronas

June 30, 2004; 6251-505-1DS

2.3.1. RAM and Registers

The DSP core has access to two RAM banks denoted

D0 and D1. All RAM addresses can be accessed in a

20-bit or a 16-bit mode via I2C bus. For fast access of

internal DSP states the processor core has an address

space of 256 data registers which also can be

accessed via I2C bus. For more details, please refer to

Section 3.3. on page 27.

2.3.2. Firmware and Software

2.3.2.1. Internal Program ROM and Firmware,

MPEG-Decoding

The firmware implemented in the program ROM of the

MAS 35x9F provides MPEG 1/2 Layer 2, MPEG 1/2/

2.5 Layer 3 and MPEG 2 AAC-decoding as well as a

G.729 encoder and decoder.

The DSP operating system starts the firmware in the

“Application Selection Mode”. By setting the appropri-

ate bit in the Application Select memory cell (see

Table 3–8 on page 32), the MPEG audio decoder or

the G.729 Codec can be activated.

The MPEG decoder provides an automatic standard

detection mode. If all MPEG audio decoders are

selected, the Layer 2, Layer 3 or AAC bit stream is rec-

ognized and decoded automatically.

To add/remove MPEG layers while running in MPEG

decoding mode (e.g. Layer 2, Layer 3 (0x0c) to

Layer 2, Layer 3, AAC (0x1c)), the application selec-

tion has to be reset before writing the new value.

For general control purposes, the operation system

provides a set of I2C instructions that give access to

internal DSP registers and memory areas.

An auxiliary digital volume control and mixer matrix is

applied to the digital stereo audio data. This matrix is

capable of performing the balance control and a sim-

ple kind of stereo basewidth enhancement. All four

factors LL, LR, RL, and RR are adjustable, please

refer to Fig. 3–3 on page 44.

2.3.2.2. Program Download Feature

The standard functions of the MAS 35x9F can be

extended

substituted

downloading

4 kWords (1 Word = 20 bits) of program code and

additionally up to 4 kWords of coefficients into the

internal RAM.

Fig. 2–2: Encoder signal flow

Fig. 2–3: Decoder signal flow

OUT

A/D

Audio

Proc.

D/A

Encoder

MIX

PIO

SDI

LINE IN

MIC IN

OUT

A/D

Audio

Proc.

D/A

Decoder

MIX

SDO

S/PDIF

PIO

SDIB

LINE IN

DSP

Volume

Matrix

MIC IN

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