5-4

FAST AND LS TTL DATA

SN54/74LS168

• SN54/74LS169

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

VIL

Input LOW Voltage

74

0.8

V

pg

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65

– 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

54

2.5

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

VOH

Output HIGH Voltage

74

2.7

3.5

V

CC

, OH

,

IN

IH

or VIL per Truth Table

VOL

Output LOW Voltage

54, 74

0.25

0.4

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN =VIL or VIH

VOL

Output LOW Voltage

74

0.35

0.5

V

IOL = 8.0 mA

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

Other Inputs

CET Input

20

40

µA

VCC = MAX, VIN = 2.7 V

IIH

Other Input

CET Input

0.1

0.2

mA

VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

Other Input

CET Input

– 0.4

– 0.8

mA

VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

–20

– 100

mA

VCC = MAX

ICC

Power Supply Current

34

mA

VCC = MAX

Note 1: Not more than one output should be shorted at one time, nor for more than 1 second.

FUNCTIONAL DESCRIPTION

The SN54/74LS168 and SN54/74LS169 use edge-

triggered D-type flip-flops that have no constraints on

changing the control or data input signals in either state of the

Clock. The only requirement is that the various inputs attain

the desired state at least a set-up time before the rising edge of

the clock and remain valid for the recommended hold time

thereafter.

The parallel load operation takes precedence over the other

operations, as indicated in the Mode Select Table. When PE is

LOW, the data on the P0–P3 inputs enters the flip-flops on the

next rising edge of the Clock. In order for counting to occur,

both CEP and CET must be LOW and PE must be HIGH. The

U/D input then determines the direction of counting.

The Terminal Count (TC) output is normally HIGH and goes

LOW, provided that CET is LOW, when a counter reaches zero

in the COUNT DOWN mode or reaches 15 (9 for the

SN54/74LS168) in the COUNT UP mode. The TC output state

is not a function of the Count Enable Parallel (CEP) input level.

The TC output of the SN54/74LS168 decade counter can also

be LOW in the illegal states 11, 13 and 15, which can occur

when power is turned on or via parallel loading. If illegal state

occurs, the SN54/74LS168 will return to the legitimate

sequence within two counts. Since the TC signal is derived by

decoding the flip-flop states, there exists the possibility of

decoding spikes on TC. For this reason the use of TC as a

clock signal is not recommended.

MODE SELECT TABLE

PE

CEP

CET

U/D

Action on Rising Clock Edge

L

X

X

X

Load (Pn

→ Qn)

H

L

L

H

Count Up (increment)

H

L

L

L

Count Down (decrement)

H

H

X

X

No Change (Hold)

H

X

H

X

No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial