5-4

FAST AND LS TTL DATA

SN54/74LS390

• SN54/74LS393

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

VIL

Input LOW Voltage

74

0.8

V

pg

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65

– 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

54

2.5

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

VOH

Output HIGH Voltage

74

2.7

3.5

V

CC

, OH

,

IN

IH

or VIL per Truth Table

VOL

Output LOW Voltage

54, 74

0.25

0.4

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN =VIL or VIH

VOL

Output LOW Voltage

74

0.35

0.5

V

IOL = 8.0 mA

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

20

µA

VCC = MAX, VIN = 2.7 V

IIH

Input HIGH Current

0.1

mA

VCC = MAX, VIN = 7.0 V

I

I

LOW C

MR

– 0.4

mA

V

MAX V

0 4 V

IIL

Input LOW Current

CP, CP0

– 1.6

mA

VCC = MAX, VIN = 0.4 V

CP1

– 2.4

mA

IOS

Short Circuit Current (Note 1)

–20

– 100

mA

VCC = MAX

ICC

Power Supply Current

26

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Sb l

P

Limits

Ui

T

C

di i

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

CP0 to Q0

25

35

MHz

C15 F

fMAX

Maximum Clock Frequency

CP1 to Q1

20

MHz

C15 F

tPLH

tPHL

Propagation Delay,

CP to Q0

LS393

12

13

20

20

ns

C15 F

tPLH

tPHL

CP0 to Q0

LS390

12

13

20

20

ns

C15 F

tPLH

tPHL

CP to Q3

LS393

40

40

60

60

ns

CL = 15 pF

tPLH

tPHL

CP0 to Q2

LS390

37

39

60

60

ns

L

p

tPLH

tPHL

CP1 to Q1

LS390

13

14

21

21

ns

tPLH

tPHL

CP1 to Q2

LS390

24

26

39

39

ns

tPLH

tPHL

CP1 to Q3

LS390

13

14

21

21

ns

tPHL

MR to Any Output

LS390/393

24

39

ns