The MAX9425/MAX9427 have internal 50

Ω series-out-

put termination resistors and 8mA internal pulldown

current sources, removing the need for external termi-

nation. The MAX9424/MAX9426 have open-emitter out-

puts, which require external termination (see the Output

Termination section).

Enable

Setting EN = high and EN = low enables the device.

Alternatively, setting EN = low and EN = high forces the

outputs to a differential low; all changes on CLK, SEL,

and IN_ are ignored.

Asynchronous Operation

Setting SEL = high and SEL = low enables the four chan-

nels to operate independently. The clock signal is

ignored in this mode. When asynchronous mode is

selected, drive or bias the CLK and CLK inputs. Biasing

the clock inputs properly is shown in Figure 5. This pre-

vents the unused clock inputs from toggling, which elimi-

nates unnecessary switching noise.

Lowest Jitter Quad PECL-to-ECL

Differential Translators

8

_______________________________________________________________________________________

80%

20%

20%

80%

DIFFERENTIAL OUTPUT

WAVEFORM

IN_

IN_

OUT_

OUT_

OUT_ - OUT_

SEL = HIGH

EN = HIGH

Figure 3. IN to OUT Propagation Delay and Transition Timing Diagram

CLK

CLK

IN_

IN_

OUT_

OUT_

SEL = LOW

EN = HIGH

Figure 4. CLK to OUT Propagation Delay Timing Diagram