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SN74LS251 数据表(PDF) 2 Page - ON Semiconductor |
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SN74LS251 数据表(HTML) 2 Page - ON Semiconductor |
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2 / 8 page ![]() SN74LS251 http://onsemi.com 2 CONNECTION DIAGRAM DIP (TOP VIEW) Select Inputs Output Enable (Active LOW) Inputs Multiplexer Inputs Multiplexer Output Complementary Multiplexer Output S0 – S2 E0 I0 – I7 Z Z 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 U.L. 65 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 U.L. 15 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. HIGH LOW (Note a) LOADING PIN NAMES LOGIC DIAGRAM 14 1 2 6 7 3 4 5 9 11 12 10 13 15 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS S2 S1 S0 E1 ZZ I0 I1 I2 I3 I4 I5 I6 I7 14 13 12 11 10 9 1234 5 6 7 16 15 8 VCC I3 I4 I5 I6 I7 S1 S0 S2 I2 I1 I0 ZZ E0 GND |
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