SN74LS76A

http://onsemi.com

2

LOGIC DIAGRAM

Q

J

CLOCK (CP)

K

Q

LOGIC SYMBOL

16

1

4

15

14

KQ

CP

JQ

GND = PIN 13

12

6

9

11

10

KQ

CP

JQ

7

2

3

8

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

Input Clamp Diode Voltage

– 0.65

– 1.5

V

Output HIGH Voltage

2.7

3.5

V

Output LOW Voltage

0.25

0.4

V

Output LOW Voltage

0.35

0.5

V

per Truth Table

I

Input HIGH Current

J, K

Clear

Clock

20

60

80

µA

Input HIGH Current

J, K

Clear

Clock

0.1

0.3

0.4

mA

Input LOW Current

J, K

Clear, Clock

– 0.4

– 0.8

mA

Short Circuit Current (Note 1)

–20

–100

mA

Power Supply Current

6.0

mA

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Maximum Clock Frequency

30

45

MHz

V

50 V

Clock Clear Set to Output

15

20

ns

PLH

Clock, Clear, Set to Output

15

20

ns

15 F

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Clock Pulse Width High

20

ns

Clear Set Pulse Width

25

ns

Setup Time

20

ns

Hold Time

0

ns