6

Hardware design

Note:

•

All unused pins should be left floating; do not ground

•

All GND pins must be well grounded

•

The area around the module should be free of any ground planes, power planes, trace routings, or metal

for 6 mm from the module antenna position, in all directions.

•

Traces should not be routed underneath the module

6.1

Reset circuitry

The BlueNRG-M2 module requires an external reset circuitry to ensure proper operation at power-on. Refer to the

"Reset management" section of the BlueNRG-2 datasheet for details.

If reset pin is controlled by an external host, RC circuit on the RESETn line is not required.

6.2

Debug interface

The BlueNRG-M2 embeds the ARM serial wire debug (SWD) port. It is two pin (clock and single bi-directional

data) debug interface, providing all the debug functionality plus real time access to system memory without halting

the processor or requiring any target resident code

Pin functionality

Module PIN

Pin description

SWCLK

12

SWD clock signal

SWDIO

13

SWD data signal

For more information refer to the BlueNRG-2 technical documentation (https://www.st.com).

BlueNRG-M2

Hardware design

DS13053 - Rev 2

page 13/30