LP8733 datasheet(33/85 Pages) TI

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V(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

PGOOD pin

EN pin

VOUT (Buck1)

VOUT (LDO0)

Buck1 internal powergood

LDO0 internal powergood

Active

Buck1 internal enable

LDO0 internal enable

4ms

2ms

LP8733-Q1

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SNVSB64 – SEPTEMBER 2018

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Figure 19. PGOOD Pin Operation in Continuous Mode

7.3.8.2 Warnings for Diagnosis (Interrupt)

7.3.8.2.1

Output Power Limit

The Buck regulators have programmable output peak current limits. The limits are individually programmed for

both regulators with BUCKx_ILIM[2:0] bits in BUCKx_CTRL_2 register. The current limit settings of master and

slave regulators used for the same output voltage rail must be identical. If the load current is increased so that

the current limit is triggered, the regulator continues to regulate to the limit current level (peak current regulation).

The voltage may decrease if the load current is higher than limit current. If the current regulation continues for 20

µs, the LP8733xx-Q1 device sets the BUCKx_ILIM_INT bit in INT_BUCK register and pulls the nINT pin low. The

host processor can read BUCKx_ILIM_STAT bits in BUCK_STAT register to see if the regulator is still in peak

current regulation mode and the interrupt is cleared by writing 1 to BUCKx_ILIM_INT bit. The current limit

interrupt can be masked by setting BUCKx_ILIM_MASK bit in BUCK_MASK register to 1. The Buck overload

situation is shown in Figure 20.

LP8733 数据表(PDF) 33 Page - Texas Instruments

LP8733 数据表(HTML) 33 Page - Texas Instruments

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