R5F56517FDFB datasheet(2/246 Pages) RENESAS

2 / 246 page

RX65N Group, RX651 Group

1. Overview

R01DS0276EJ0230 Rev.2.30

Page 2 of 246

Jun 20, 2019

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different

packages.

Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the

modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details,

see Table 1.2, Code Flash Memory Capacity and Comparison of Functions for Different Packages.

Table 1.1

Outline of Specifications (1/10)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 120 MHz

 32-bit RX CPU (RXv2)

 Minimum instruction execution time: One instruction per state (cycle of the system

clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 Basic instructions: 75

 Floating-point instructions: 11

 DSP instructions: 23

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32 / 32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory

Code flash memory

 Capacity: 512 Kbytes/768 Kbytes/1 Mbyte/1.5 Mbytes/2 Mbytes

 50 MHz  No-wait cycle access

100 MHz

 1-wait cycle access

100 MHz

 2-wait cycle access

 Instructions hitting the ROM cache or operand = 120 MHz: No-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

 Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

 A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory

 Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID

 16-byte unique ID for the device

RAM

 Capacity: 256 Kbytes (Products with 1 Mbyte of code flash memory or less)

RAM: 256 Kbytes

 Capacity: 640 Kbytes (Products with at least 1.5 Mbytes of code flash memory)

RAM: 256 Kbytes

Expansion RAM: 384 Kbytes

 120 MHz, no-wait access

Standby RAM

 Capacity: 8 Kbytes

 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

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