Capture Timers 1/2
16
PRELIMINARY V1.8
9.2.
Auto-Reload Mode
If the CT1MD[2:0] bits in the CT1CR are 000, the C-Timer1 will operate in the Auto-
Reload Mode.
If the CT2MD[1:0] bits in the CT2CR are 00, the C-Timer2 will operate in the Auto-
Reload Mode.
A C-Timer has 8 counting clocks that can be selected by CT1FS[2:0] (or CT2FS[2:0]).
The period of the Fsys/12 clock is one machine cycle or one fastest instruction cycle.
This clock will be run during any power-saving mode except the StopAll mode. During
the FastAll or FastPeri mode, the Fsys/12 clock is equal to Ffast/12. During the SlowAll
or SlowPeri mode, the Fsys/12 clock is equal to Fslow/12. The Ffast/2
4, F
fast/2
5, F
fast/2
7,
Ffast/2
10, F
fast/2
14, and F
fast/2
18 can be used during the FastAll or FastPeri mode only.
Two external interrupt pins(CPTRU1 and CPTRU2) are connected to the C-Timer1 and
2. Thus, the timers can be used as the Event Counters. To use this timer as an Event
Counter, the CPTRU1 (or CPTRU2) should be assigned as an input port by the port
control register.
After the CT1EN(or CT2EN) bit is set to high, the CT1CNTH & CT1CNTL (or
CT2CNTH & CT2CNTL) will start to count up the negative edge of a selected input
clock. When the CT1EN (or CT2EN) bit is low, the Match signal is never generated
even though the contents of the CT1DATH & CT1DATL (or CT2DATH & CT2DATL)
and CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) are the same. In Auto-
Reload Mode, CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) act as a 16-bit
up-counter that can be cleared by the CT1CNTLR (or CT2CNTLR) bit or by the Match
signal. The CT1CNTH & CT1CNTL (or CT2CNTH & CT2CNTL) is a modulo-N
counter (from 0 to N-1), N is the content of the CT1DATH & CT1DATL (or
CT2DATH & CT2DATL). The match signal will always set the CT1INT (or CT2INT)
bit to high. The CT1INT (or CT2INT) bit can be cleared by a C-Timer Interrupt
Acknowledge or software.
9.3.
Up Down-Count Mode
If the CT1MD[2:0] bits in the CT1CR are 1XX (X means don’t care), the C-Timer1 will
operate in the Up Down-Count Mode.
After the CT1EN bit is set to high, the 16-bit up down-counter(CT1CNTH &
CT1CNTL) will start to count. It counts up on the negative edge of CPTRU1 and counts
down on the negative edge of CPTRD1. To use CPTRU1, CT1FS[5:3] must set to 111.
In Up Down-Count Mode, CT1CNTH & CT1CNTL act as a 16-bit up down-counter
that can be cleared by the CT1CNTLR bit. The CT1CNTH & CT1CNTL is a modulo-
65536 counter (from 0 to 65535). The overflow signal will set the CT1OV bit in CT1SR
to high and the underflow signal will set the CT1UN bit in CT1SR to high. Both the
overflow and underflow signal will always set the CT1INT bit in INT2 register and
CT1OVUN bit in CT1SR to high. The CT1INT bit can be cleared by a C-Timer
Interrupt Acknowledge or software, and CT1OV, CT1UN and CT1OVUN can be
cleared by reading the CT1SR. Another Capture-Timer1 interrupt will not be generated
if CT1OVUN is still not being cleared.
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