STM32L552CEU6PTR datasheet(267/340 Pages) STMICROELECTRONICS

267 / 340 page

DS12737 Rev 6

267/340

STM32L552xx

Electrical characteristics

307

Table 124. DFSDM measured timing 1.71 to 3.6 V(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK

DFSDM

clock

1.71 < VDD < 3.6 V

fSYSCLK

MHz

fCKIN

(1/TCKIN)

Input clock

frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < VDD < 3.6 V

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

1.71 < VDD < 3.6 V

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

2.7 < VDD < 3.6 V

fCKOUT

Output

clock

frequency

1.71 < VDD < 3.6 V

DuCyCKOUT

Output

clock

frequency

duty cycle

1.71 < VDD < 3.6 V

twh(CKIN)

twl(CKIN)

Input clock

high and

low time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

TCKIN/2-0.5

TCKIN/2

tsu

Data input

setup time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

Data input

hold time

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

2.5

TManchester

Manchester

data period

(recovered

clock

period)

Manchester mode

(SITP[1:0]=2,3),

Internal clock mode

(SPICKSEL[1:0]

≠0),

1.71 < VDD < 3.6 V

(CKOUTDIV

+1) *

TDFSDMCLK

(2*CKOUTDI

V) *

TDFSDMCLK

1. Data based on characterization results, not tested in production.

STM32L552CEU6PTR 数据表(PDF) 267 Page - STMicroelectronics

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STM32L552CEU6PTR 数据表(PDF) 267 Page - STMicroelectronics

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