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STM32L552CEU6PTR 数据表(PDF) 286 Page - STMicroelectronics |
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STM32L552CEU6PTR 数据表(HTML) 286 Page - STMicroelectronics |
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286 / 340 page  Electrical characteristics STM32L552xx 286/340 DS12737 Rev 6 Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 140 through Table 143 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable • MemoryType = FMC_MemoryType_CRAM • WriteBurst = FMC_WriteBurst_Enable • CLKDivision = 1 • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Table 138. Asynchronous multiplexed PSRAM/NOR write timings(1) 1. Guaranteed by characterization results, not tested in production. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 5THCLK-0.5 5THCLK+1 ns tv(NWE_NE) FMC_NEx low to FMC_NWE low THCLK– 0.5 THCLK+ 1 tw(NWE) FMC_NWE low time 2THCLK-0.5 2THCLK+0. 5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2THCLK-0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 3 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1 tw(NADV) FMC_NADV low time THCLK+0.5 THCLK+1.5 th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) THCLK-3 - th(A_NWE) Address hold time after FMC_NWE high Address holded until next write operation - th(BL_NWE) FMC_BL hold time after FMC_NWE high 2THCLK-0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - THCLK tv(Data_NADV) FMC_NADV high to Data valid - THCLK+2 th(Data_NWE) Data hold time after FMC_NWE high 2THCLK+0.5 - Table 139. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) 1. Guaranteed by characterization results, not tested in production. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 10THCLK-0.5 10THCLK+1 ns tw(NWE) FMC_NWE low time 7THCLK-0.5 7THCLK+0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 7THCLK+11.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5THCLK+12.5 - |
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