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STM32L412RBI6XXX 数据表(PDF) 126 Page - STMicroelectronics |
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STM32L412RBI6XXX 数据表(HTML) 126 Page - STMicroelectronics |
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126 / 192 page  Electrical characteristics STM32L412xx 126/192 DS12469 Rev 8 6.3.9 PLL characteristics The parameters given in Table 61 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 21: General operating conditions. Table 61. PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(2) -4 - 16 MHz PLL input clock duty cycle - 45 - 55 % fPLL_P_OUT PLL multiplier output clock P Voltage scaling Range 1 3.0968 - 80 MHz Voltage scaling Range 2 3.0968 - 26 fPLL_Q_OUT PLL multiplier output clock Q Voltage scaling Range 1 12 - 80 MHz Voltage scaling Range 2 12 - 26 fPLL_R_OUT PLL multiplier output clock R Voltage scaling Range 1 12 - 80 MHz Voltage scaling Range 2 12 - 26 fVCO_OUT PLL VCO output Voltage scaling Range 1 96 - 344 MHz Voltage scaling Range 2 96 - 128 tLOCK PLL lock time - - 15 40 μs Jitter RMS cycle-to-cycle jitter System clock 80 MHz -40 - ±ps RMS period jitter - 30 - IDD(PLL) PLL power consumption on VDD(1) VCO freq = 96 MHz - 200 260 μA VCO freq = 192 MHz - 300 380 VCO freq = 344 MHz - 520 650 1. Guaranteed by design. 2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between the 2 PLLs. |
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