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STM32L552CEU6PXXX 数据表(PDF) 42 Page - STMicroelectronics |
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STM32L552CEU6PXXX 数据表(HTML) 42 Page - STMicroelectronics |
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42 / 340 page  Standby LPR Powered Off Off SRAM2 ON LSE LSI BOR, RTC, IWDG *** All other peripherals are powered off *** I/O configuration can be floating, pull-up or pull-down Reset pin 5 I/Os (WKUPx)(9) BOR, RTC, IWDG OFF Powered Off Shutdown OFF Powered Off Off Powered Off LSE RTC *** All other peripherals are powered off *** I/O configuration can be floating, pull-up or pull-down(10) Reset pin 5 I/Os (WKUPx)(9) RTC 1. LPR means Main regulator is OFF and Low-power regulator is ON. 2. All peripherals can be active or clock gated to save power consumption. 3. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM. 4. The SRAM1 and SRAM2 clocks can be gated on or off independently. 5. SMPS mode can be used in Stop 0 mode, but no significant power gain can be expected. 6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event. 7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match. 8. USB_FS wakeup by resume from suspend and attach detection protocol event. 9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5. 10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode. Table 10. STM32L552xx modes overview (continued) Mode Regulator and SMPS mode(1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source |
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