STPD01PUR datasheet(3/43 Pages) STMICROELECTRONICS

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Pin configuration (top through view)

Figure 2. Pin configuration (top through view)

Table 2. Pin description

Position

Name

Description

SDA

I2C data

SCL

I2C clock

ADD

I2C address selection (cannot be left floating)

INT

Interrupt pin (open drain output)

Enable pin. Internally pulled up to VREG

VDRIVEH High-side driver supply. Connect to a bypass capacitor

VCC

Analog supply input

PVIN

Power supply input

PVIN

Power supply input

PGND

Power ground

PGND

Power ground

PGND

Power ground

Switching node

BOOT

Connect the bootstrap capacitor (0.1 µF) between this pin and LX

Pon

Power-on (open drain output). Pulled high when Vout reaches the regulation value after startup

VREG

Internal LDO regulator voltage pin (connect 1 μF capacitor between this pin and GND)

ISNS+

Positive connection for the current sensing resistor. Connect to GND if not used

ISNS-

Negative connection for the current sensing resistor. Connect to GND if not used

VSNS

Output voltage sensing pin. Used also for cable drop compensation see Section 7.2 Cable drop

compensation

CDC

Cable drop compensation programming pin

STPD01

Pin configuration (top through view)

DS13473 - Rev 1

page 3/43

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