ZSC31150 Datasheet

© 2016 Integrated Device Technology, Inc.

14

December 6, 2016

The result of the AD conversion is a relative counter result corresponding to the following equation (see the ZSC31150 Functional Description

for more detailed equations):





















ADC

ADC_REF

ADC_DIFF

r

ADC

RS

V

V

2

Z

ADC

Number of counts (result of the conversion)

Selected ADC resolution in bits

EEPROM setting)

Table 2.3 Analog Output Resolution versus Sample Rate

ADC

Adjustment

Approximated Output

Resolution [a]

Sample Rate

fCON [b]

Averaged

ADC Order

Digital

Analog

[Bit]

[Bit]

[Bit]

[Hz]

[Hz]

[Hz]

[Hz]

1

13

13

12

345

460

130

172

14

14

12

178

237

67

89

15

14

12

90

120

34

45

16

14

12

45

61

17

23

2

13

13

12

5859

7813

2203

2937

14

14

12

3906

5208

1469

1958

15

14

12

2930

3906

1101

1468

16

14

12

1953

2604

734

979

[a] The ADC resolution should be one bit higher than the required output resolution if the AFE gain is adjusted so that more than 50% of the input

range is used. Otherwise the ADC resolution should be more than one bit higher than the required output resolution.

[b] The sampling rate (A/D conversion time) is only a part of the whole cycle; refer to the ZSC31150 Bandwidth Calculation Spreadsheet for

detailed information.

Note:

reference voltage.

specified accuracy, stability, and nonlinearity parameters of the AFE. This condition is also valid for whole temperature range and all

applicable sensor tolerances. The ZSC31150 does not have an internal failsafe function that verifies that the input meets this condition.