month s

(

)

=

4.6

Capacitive load

Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain

peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that

with a gain peaking higher than 2.3 dB an op amp might become unstable.

Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.

Figure 38. Stability criteria with a serial resistor at different supply voltages shows the serial resistor that must be

added to the output, to make a system stable. Figure 39. Test configuration for Riso shows the test configuration

using an isolation resistor, Riso.

10

2

10

3

10

4

10

5

10

6

0.1

1

10

100

@Vcc=4V

@Vcc=12V

@Vcc=36V

Stable

Vcc=36V

Vicm=18V

follower

configuration

T=25°C

Capacitive load (pF)

Unstable

Cload

VIN

+

-

VCC+

Riso

10 kΩ

VCC-

VOUT

4.7

PCB layout recommendations

Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power

supply. The power and ground traces are critical as they must provide adequate energy and grounding for all

circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic

inductance.

In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that connects the

bottom and top layer ground planes together in many locations is often used.

The copper traces that connect the output pins to the load and supply pins should be as wide as possible to

minimize trace resistance.

TSB571, TSB572

Capacitive load

DS11248 - Rev 7

page 19/31