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TMP139AIYAHR 数据表(PDF) 25 Page - Texas Instruments

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部件名 TMP139AIYAHR
功能描述  TMP139 0.5 째C Accuracy, JEDEC DDR5 Grade B, Digital Temperature Sensor With I2C and I3C Interface
PDF  58 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMP139AIYAHR 数据表(HTML) 25 Page - Texas Instruments

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0x80
T
0x00
Sr or P
T
S or Sr
1
1
1
1
1
1
0
ENINT
ACK/NACK
R/W=0
PEC
T
PEC
T
Sr
0
SA
1
0
HID2
HID1
HID0
ACK/NACK
R/W=0
Figure 7-28. ENEC CCC Direct with PEC Enabled
Note
TMP139 NACKs the ENEC CCC if the previous transaction has a parity or PEC error and the host
starts the transaction with a Repeated Start.
7.4.6.2 DISEC CCC
The DISEC CCC is issued by the host controller to disable the event interrupt generation. The CCC takes effect
after a Stop has been issued by the host controller. Once the DISEC is received, the TMP139 shall the update
MR27 register bit IBI_ERROR_EN to 1'b0.
Note
It is illegal for the host controller to send the DISINT bit as 0.
The command may be issued either as a broadcast command or as a direct command to a specific device as
shown in Figure 7-29 and Figure 7-30.
0x01
T
0x00
Sr or P
T
S or Sr
1
1
1
1
1
1
0
DISINT
ACK/NACK
R/W=0
Figure 7-29. DISEC CCC Broadcast
0x81
T
0x00
Sr or P
T
S or Sr
1
1
1
1
1
1
0
DISINT
ACK/NACK
R/W=0
Sr
0
SA
1
0
HID2
HID1
HID0
ACK/NACK
R/W=0
Figure 7-30. DISEC CCC Direct
The command may be issued either as a broadcast or as a direct command, as shown in Figure 7-31 and Figure
7-32, with PEC Enabled. In such a case the host controller shall append the PEC byte calculated on all bytes
except the byte with 7'h7E and R/W=0 after the Start or Repeated Start.
0x01
T
0x00
Sr or P
T
S or Sr
1
1
1
1
1
1
0
DISINT
ACK/NACK
R/W=0
PEC
T
Figure 7-31. DISEC CCC Broadcast with PEC Enabled
www.ti.com
TMP139
SNIS217 – DECEMBER 2020
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMP139



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