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TMP139AIYAHT 数据表(PDF) 27 Page - Texas Instruments

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部件名 TMP139AIYAHT
功能描述  TMP139 0.5 째C Accuracy, JEDEC DDR5 Grade B, Digital Temperature Sensor With I2C and I3C Interface
PDF  58 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMP139AIYAHT 数据表(HTML) 27 Page - Texas Instruments

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0x29
T
Sr or P
S or Sr
1
1
1
1
1
1
0
ACK
R/W=0
Figure 7-35. SETAASA CCC
Note
TMP139 NACKs the SETAASA CCC if the previous CCC transaction has a parity error and the host
starts the transaction with a Repeated Start.
7.4.6.5 GETSTATUS CCC
The GETSTATUS CCC is issued by the host controller to the TMP139 to get the status of any pending parity
error, PEC error, or interrupt event. Once the GETSTATUS is received, the TMP139 shall not clear the status
and host must issue additional transactions on the bus to clear the status flags individually or by writing 1'b1 to
the MR27 register CLR_GLOBAL bit.
The command is issued only in direct mode as shown in Figure 7-36, when PEC is disabled, and in Figure 7-37,
when PEC is enabled. In the latter case, the host controller shall append the PEC byte calculated on all bytes
except the byte with 7'h7E and R/W=0 after the Start or Repeated Start. The TMP139 calculates the PEC on the
data bytes that are sent to the host.
0x90
T
T=1
S or Sr
1
1
1
1
1
1
0
ACK/NACK
R/W=0
Sr
0
SA
1
0
HID2
HID1
HID0
ACK/NACK
R/W=1
PEC_Err
0
0
0
0
0
0
0
Sr or P
T=0
0
0
P_Err
0
PENDIN G INTERRUPT
Figure 7-36. GETSTATUS CCC Direct
0x90
T
T=1
S or Sr
1
1
1
1
1
1
0
ACK/NACK
R/W=0
Sr
0
SA
1
0
HID2
HID1
HID0
ACK/NACK
R/W=1
PEC_Err
0
0
0
0
0
0
0
Sr or P
T=0
0
0
P_Err
0
PENDIN G INTERRUPT
PEC
T
PEC
T=1
Figure 7-37. GETSTATUS CCC Direct with PEC Enabled
Note
TMP139 NACKs the GETSTATUS CCC if the previous transaction has a parity or PEC error and the
host starts the transaction with a Repeated Start.
7.4.6.6 DEVCAP CCC
The DEVCAP CCC is issued by the host controller to the TMP139, to get the optional device capabilities that are
supported as given in Table 7-7.
The command is issued only in direct mode as shown in Figure 7-38, when PEC is disabled, and in Figure 7-39,
when PEC is enabled. In the latter case the host controller shall append the PEC byte calculated on all bytes
www.ti.com
TMP139
SNIS217 – DECEMBER 2020
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMP139



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