TSC2012 datasheet(53/54 Pages) STMICROELECTRONICS

53 / 54 page

Figure 50.

Noise vs. frequency................................................................ 22

Figure 51.

ON/OFF delay for shutdown mode ..................................................... 23

Figure 52.

Output voltage vs. Vsense beyond the sense operating ....................................... 23

Figure 53.

Power up time delay ............................................................... 23

Figure 54.

Power supply when Vicm > Vcc ........................................................ 24

Figure 55.

Input bias current vs. common mode voltage Vcc = 5 V ....................................... 25

Figure 56.

Power supply when Vicm < Gnd ....................................................... 26

Figure 57.

Vref powered by an external voltage source ............................................... 26

Figure 58.

Output reference to ground .......................................................... 28

Figure 59.

Output reference to Vcc ............................................................. 28

Figure 60.

Split supply ..................................................................... 29

Figure 61.

External supply................................................................... 30

Figure 62.

Schematic for Vocm error ............................................................ 32

Figure 63.

Input current..................................................................... 33

Figure 64.

SHDN pin ...................................................................... 35

Figure 65.

Capacitive load response at Vcc = 3.3 V.................................................. 35

Figure 66.

Capacitive load response at Vcc = 3.3 V with a step of 100 mV .................................. 36

Figure 67.

RC filter when driving ADC........................................................... 36

Figure 68.

Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter .................................. 37

Figure 69.

Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter .................................. 37

Figure 70.

Stability criteria with a serial resistor at VCC = 5 V ........................................... 37

Figure 71.

Start-up time with a decoupling capacitance of 100 nF........................................ 38

Figure 72.

Recommended layout .............................................................. 39

Figure 73.

EMIRR on pin+ ................................................................... 39

Figure 74.

EMIRR on pin- ................................................................... 39

Figure 75.

EMIRR on pin+ (TSC2010) .......................................................... 40

Figure 76.

EMIRR on pin- (TSC2010) ........................................................... 40

Figure 77.

Negative overvoltage recovery VCC = ± 2.5 V .............................................. 41

Figure 78.

Positive overvoltage recovery VCC = ± 2.5 V............................................... 41

Figure 79.

Half-bridge application .............................................................. 42

Figure 80.

TSC2011 H Bridge application ........................................................ 43

Figure 81.

Solenoid valve application ........................................................... 44

Figure 82.

SO8 package outline ............................................................... 46

Figure 83.

MiniSO8 package outline ............................................................ 47

TSC2010, TSC2011, TSC2012

List of figures

DS13057 - Rev 4

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