VIPER317LDTR datasheet(19/40 Pages) STMICROELECTRONICS

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If VUVP falls below VUVP_th, the DEB counter is incremented. If VUVP increases above VUVP_th before uvp_eoc

is reached, the counter is decremented. If the count goes back down to zero, a disturbance on the UVP pin is

assumed and there is no consequence on the IC behavior.

If VUVP stays below VUVP_th until the counter reaches deb_eoc: the device is disabled; most of the internal blocks

are turned off and the internal consumption is reduced to Iq_DIS; VCC is maintained between VCson and VCcon

by the periodical activation of the internal HV-current source; the DEB counter is reset. Of course, if during the

count-up VUVP exceeds VUVP_th for some time, the DEB counter is decremented during that time and the IC

disable is delayed accordingly.

With IC disabled: if VUVP rises above VUVP_th, the REST counter is incremented, and when it reaches rest_eoc

(corresponding to tUVP_REST), the IC resumes switching. Of course, if during the count-up, VUVP falls below

VUVP_th for some time, the REST counter is decremented during that time and the IC re-enabling is delayed

accordingly.

Figure 29. UVP timing

VUVP

REST counter

IDRAIN

rest_eoc

VUVP_th

VDD

IC re-enabled

IC disabled

normal operation

disabled with ultra-low consumption (Iq_DIS)

normal operation

tUVP_REST

Restart

delay

VCCon

VCSon

DEB counter

tUVP_DEB

< tUVP_DEB

deb_eoc

An input undervoltage protection can be easily realized connecting the rectified mains to UVP pin through a

voltage divider, as shown in Figure 30. Connection for input undervoltage protection/disable (isolated or non-

isolated topologies).

VIPER31

Undervoltage protection

DS13285 - Rev 3

page 19/40

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