VIPER317HDTR datasheet(21/40 Pages) STMICROELECTRONICS

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Figure 31. Hold-up in case of input line missing cycles

VUVP_th

1 missing cycle

VBULK

tUVP_DEB

VUVP

tUVP_DEB

2 missing cycles

IDRAIN

IC disabled

here

4.13

Overvoltage protection

If the voltage across OVP pin (VOVP) exceeds the internal threshold VOVP_th (4 V typ.) for a time greater than

tOVP_DEB (250 us, typ.), the PWM is disabled in autorestart for tOVP_REST time (500 ms, typ.), until VOVP falls

below VOVP_th.

The time interval tOVP_DEB is intended to filter out possible noises/disturbances of the line, which could affect the

correct operation of the function, and is obtained through an up/down counter, where tOVP_DEB is the time the

counter needs to reach its end-of-count (ovp_eoc) starting from zero and counting always up.

The operation is shown in Figure 32. OVP timing. When VOVP exceeds VOVP_th, the up/down OVP counter is

incremented.

If VOVP falls below VOVP_th before the OVP counter reaches ovp_eoc, the counter is decremented. If the count

goes down to zero, a disturbance on the OVP pin is assumed and there is no consequence on the IC behavior.

If VOVP stays above VOVP_th until the OVP counter reaches ovp_eoc: the PWM is disabled in autorestart for a

tOVP_REST time interval; the OVP counter is reset; VCC is maintained between VCson and VCcon by the periodical

activation of the internal HV-current source. Of course, if during the count-up VOVP falls below VOVP_th for some

time, during that time the counter is decremented and the PWM disable is delayed accordingly.

When VOVP drops below VOVP_th, the IC waits for the end of tOVP_REST, then restarts with soft-start phase.

VIPER31

Overvoltage protection

DS13285 - Rev 3

page 21/40

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