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5000 数据表(PDF) 13 Page - Renesas Technology Corp |
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5000 数据表(HTML) 13 Page - Renesas Technology Corp |
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13 / 21 page ![]() F2932 F2932, Rev 1 05/12/2016 13 High Reliability SP2T RF Switch PIN DIAGRAM VDD 1 4 3 2 RFC GND GND VCTL E.P. 12 9 10 11 RF1 GND RF2 50Ω 50Ω PIN DESCRIPTION PIN NAME FUNCTION 1 VDD Power Supply. Bypass to GND with capacitors shown in the Typical Application Circuit as close as possible to pin. 2 VCTL Controls the selected path when EN is low. Is disabled when EN is logic high. See Table 1. 3 RFC RF Common Port. Matched to 50 Ω when one of the 2 RF ports is selected. If this pin is not 0 V DC, then an external coupling capacitor must be used. 4, 6, 7, 8, 10, 11, 13, 14, 15, 16 GND Ground. Also, internally connected to the ground paddle. Ground this pin as close to the device as possible. 5 EN EN as a logic low allows VCTL to control the selected switch path. With EN set to logic high puts the part in all paths off state and disables the control of VCTL. See Table 1. 9 RF1 RF1 Port. Matched to 50 Ω. If this pin is not 0 V DC, then an external coupling capacitor must be used. 12 RF2 RF2 Port. Matched to 50 Ω. If this pin is not 0 V DC, then an external coupling capacitor must be used. 17 — EP Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device and into the PCB ground planes. These multiple ground vias are also required to achieve the specified RF performance. |
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