DSA400

DS20006356A-page 4

 2020 Microchip Technology Inc.

2.0

PIN DESCRIPTIONS

OE2

11

NC

VSS

VSS

13

12

14

VSS

4

VSS

NC

OE1

2

3

1

5

7

68

9

10

15

17

16

18

19

20

FIGURE 2-1:

Pin Configuration, 20-Pin QFN (5.0 mm x 3.2 mm)

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

Pin Name

Pin Type

Description

1

OE1

I

Output Enable for Bank1 (CLK0 and CLK3); Active-High. See

Table 3-1.

2

NC

N/A

Leave unconnected or connect to ground.

3

PWR

Ground.

4

PWR

Ground.

5

CLK0–

O

Complement output of differential pair 0 (off when in LVCMOS format).

6

CLK0+

O

True output of differential pair 0 or LVCMOS output 0.

7

CLK1–

O

Complement output of differential pair 1 (off when in LVCMOS format).

8

CLK1+

O

True output of differential pair 1 or LVCMOS output 1.

9

PWR

Power Supply for Bank2 (CLK1 and CLK2).

10

FSB2

I

Input for selecting pre-configured frequencies on Bank2 (CLK1 and

CLK2).

11

OE2

I

Output Enable for Bank2 (CLK1 and CLK2); Active-High. See

Table 3-1.

12

NC

N/A

Leave unconnected or connect to ground.

13

PWR

Ground.

14

PWR

Ground.

15

CLK2–

O

Complement output of differential pair 2 (off when in LVCMOS format).

16

CLK2+

O

True output of differential pair 2 or LVCMOS output 2.

17

CLK3–

O

Complement output of differential pair 3 (off when in LVCMOS format).

18

CLK3+

O

True output of differential pair 3 or LVCMOS output 3.

19

PWR

Power Supply for Bank1 (CLK0 and CLK3).

20

FSB1

I

Input for selecting pre-configured frequencies on Bank1 (CLK0 and

CLK3).