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ADP7118ACPZN2.5-R7 数据表(PDF) 19 Page - Analog Devices

部件名 ADP7118ACPZN2.5-R7
功能描述  20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator
PDF  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP7118ACPZN2.5-R7 数据表(HTML) 19 Page - Analog Devices

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Data Sheet
ADP7118
Rev. F | Page 19 of 24
25
35
45
55
65
75
85
95
105
115
125
135
145
0
0.1
0.2
0.3
0.4
0.5
0.6
0.8
1.0
0.7
0.9
TOTAL POWER DISSIPATION (W)
500mm2
100mm2
50mm2
TJ MAX
Figure 58. TSOT, TA = 25°C
50
140
130
120
110
100
90
80
70
60
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
TOTAL POWER DISSIPATION (W)
500mm2
100mm2
50mm2
TJ MAX
Figure 59. TSOT, TA = 50°C
65
145
75
85
95
105
115
125
135
0
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TOTAL POWER DISSIPATION (W)
500mm2
100mm2
50mm2
TJ MAX
Figure 60. TSOT, TA = 85°C
In the case where the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 61, Figure 62, and Figure 63).
Calculate the maximum junction temperature by using
Equation 2.
TJ = TB + (PD × ΨJB)
The typical value of ΨJB is 24°C/W for the 8-lead LFCSP package,
38.8°C/W for the 8-lead SOIC package, and 43°C/W for the 5-lead
TSOT package.
TOTAL POWER DISSIPATION (W)
0
20
40
60
80
100
120
140
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
Figure 61. LFCSP Junction Temperature Rise, Different Board Temperatures
TOTAL POWER DISSIPATION (W)
0
20
40
60
80
100
120
140
0
0.5
1.0
1.5
2.0
2.5
3.0
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
Figure 62. SOIC Junction Temperature Rise, Different Board Temperatures
TOTAL POWER DISSIPATION (W)
0
20
40
60
80
100
120
140
0
0.5
1.0
1.5
2.0
2.5
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
Figure 63. TSOT Junction Temperature Rise, Different Board Temperatures



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