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MPZ2012S601AT000 数据表(PDF) 27 Page - Microchip Technology |
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MPZ2012S601AT000 数据表(HTML) 27 Page - Microchip Technology |
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27 / 36 page  FIGURE B-4: EVB-KSZ9477 SCHEMATIC - KSZ9477 RGMII TO SAMA5D3 LED4_1 5 LED4_0 5 LED3_1 5 LED3_0 5 LED5_0 5 LED5_1 5 LED2_1 5 LED2_0 5 LED1_1 5 LED1_0 5 25MHz 1 3 Y3 15pF C167 15pF C168 6.04k 1% R108 Jitter Blocker 1 2 3 4 5 6 7 8 9 10 J18 1 4 2 3 SW3 2 4 VCC GND VCC GND D C D U13 74LVC1G14GW,125 PB30_RXD 6 PB31_TXD 6 GTXD0 GTXD1 GTXD2 GTXD3 GRXD0 GRXD1 GRXD2 GRXD3 GTXCK GTXCTL GTXD0 GTXD1 GTXD2 GTXD3 GRXD0 GRXD1 GRXD2 GRXD3 GTXCK GTXCTL GRXCK GRXCTL G125REFCK 3V3 10k R92 3V3 10k R95 3V3 22R R93 22R R118 3V3 GPIO filtered KSZ9477 Output Header INTRP_N VDDIOP 10k R94 SPI / I2C MOSI MOSI MISO MISO SP_CLK SCLK SCS SCS 0R R99 0R R102 I2C_SDA I2C_SCL SCLK SCLK MOSI 0R R105 0R R106 SP_MOSI SCS 3V3 SPI Activity LED 10k R100 10k DNP R104 3V3 SW_RESETN S_TX7_N 5 S_TX7_P 5 S_RX7_N 5 S_RX7_P 5 GPIO GPIO GPIO GPIO_FILT GPIO_FILT PME_N INTRP_N SYNCLKO SYNCLKO SYNCLKO 22R R101 1 2 3 4 5 6 7 8 J19 Header 4x2 PC22_SPI1_MISO 8 PC23_SPI1_MOSI 8 PC24_SPI1_SPCK 8 PC25_SPI1_NPCS0 8 MOSI MISO SCLK SCS MCU SPI LED2_0 LED4_0 LED1_0 LED1_1 LED2_1 LED4_1 LED5_1 2 3 16 4 5 1 6 15 14 13 12 11 7 10 8 9 SW2 SPST 8POS 3V3 GRXD0 4.7k R109 KSZ9477 Strapping Options LED1_0 LED1_1 LED2_0 LED2_1 LED4_0 LED4_1 LED5_1 0R DNP R96 SW_RESETN 3V3 ISET XI XO 1k R107 750R R110 750R R111 750R R112 750R R113 750R R114 750R R115 750R R116 Blue D4 0.1uF C166 200ms delay P1_TXRXA_P 5 P1_TXRXA_N 5 P1_TXRXB_P 5 P1_TXRXB_N 5 P1_TXRXC_P 5 P1_TXRXC_N 5 P1_TXRXD_P 5 P1_TXRXD_N 5 P2_TXRXA_P 5 P2_TXRXA_N 5 P2_TXRXB_P 5 P2_TXRXB_N 5 P2_TXRXC_P 5 P2_TXRXC_N 5 P2_TXRXD_P 5 P2_TXRXD_N 5 P3_TXRXA_P 5 P3_TXRXA_N 5 P3_TXRXB_P 5 P3_TXRXB_N 5 P3_TXRXC_P 5 P3_TXRXC_N 5 P3_TXRXD_P 5 P3_TXRXD_N 5 P4_TXRXA_P 5 P4_TXRXA_N 5 P4_TXRXB_P 5 P4_TXRXB_N 5 P4_TXRXC_P 5 P4_TXRXC_N 5 P4_TXRXD_P 5 P4_TXRXD_N 5 P5_TXRXA_P 5 P5_TXRXA_N 5 P5_TXRXB_P 5 P5_TXRXB_N 5 P5_TXRXC_P 5 P5_TXRXC_N 5 P5_TXRXD_P 5 P5_TXRXD_N 5 1 2 J6 VDD 4 PDB/OE/CLK1 1 REFIN 3 GND 2 CLK0 6 CSEL/CLK2 5 PL902xxxUSY U12 0R R11 To replace xtal with DSC1101 oscillator, remove XO resistor and change pin 4 resistor from GND to 3V3. 0R DNP R12 0R R126 3V3 PB0_GTX0 T2 PB1_GTX1 N7 PB2_GTX2 T3 PB3_GTX3 N6 PB4_GRX0 P5 PB5_GRX1 T4 PB6_GRX2 R4 PB7_GRX3 U1 PB8_GTXCK R5 PB9_GTXEN P3 PB10_GTXER R6 PB11_GRXCK V3 PB12_GRXDV P6 PB13_GRXER V1 PB14_GCRS R7 PB15_GCOL U3 PB16_GMDC P7 PB17_GMDIO V2 PB18_G125CK V5 PB19_GTX4 T6 PB20_GTX5 N8 PB21_GTX6 U4 PB22_GTX7 M7 PB23_GRX4 U5 PB24_GRX5 M8 PB25_GRX6 T5 PB26_GRX7 N9 PB27 V4 PB28 M9 PB29 P8 PB30 M10 PB31 R9 ATSAMA5D36A_BGA324 U7B 0.1uF C170 0.1uF C171 22R R141 22R R139 22R R145 22R R144 22R R143 22R R142 22R R134 22R R135 22R R136 22R R137 22R R138 22R R140 KSZ9477S Strap Options Open Closed GRXD0 RGMII: 1000 Mb/s RGMII: 100 Mb/s LED2_0 1000B-T master 1000B-T slave or 10/100 MDI or 10/100 MDI-X LED4_0 Enable AN Disable AN or 100B-TX or 1000B-T LED1_0 Quiet-WIRE off Quiet-WIRE on LED1_1 Flow control on Flow control off LED2_1 Normal link up Fast link up LED4_1 SPI I2C LED5_1 Start switch Don't start switch IBA IBA off IBA on No option: LED3_1 No option for MDC/MDIO RXD6_[3:2] Port 6 fixed as RGMII RXD6_1 Not relevant when port is RGMII SYNCLKO S_REFCLKP/M input clock not used 125MHz VDD 6 GND 3 EN 1 OUT 4 NC 2 NC 5 OSC1 TXRX1P_A 1 TXRX1M_A 2 LED1_0 105 LED1_1 106 TXRX1P_B 4 TXRX1M_B 5 TXRX1P_C 6 TXRX1M_C 7 TXRX1P_D 8 TXRX1M_D 9 TXRX2P_A 12 TXRX2M_A 13 LED2_0 91 LED2_1 92 TXRX2P_B 15 TXRX2M_B 16 TXRX2P_C 17 TXRX2M_C 18 TXRX2P_D 20 TXRX2M_D 21 TXRX3P_A 24 TXRX3M_A 25 LED3_0 88 LED3_1 89 TXRX3P_B 26 TXRX3M_B 27 TXRX3P_C 28 TXRX3M_C 29 TXRX3P_D 31 TXRX3M_D 32 TXRX4P_A 34 TXRX4M_A 35 LED4_0 85 LED4_1 86 TXRX4P_B 37 TXRX4M_B 38 TXRX4P_C 39 TXRX4M_C 40 TXRX4P_D 42 TXRX4M_D 43 TXRX5P_A 112 TXRX5M_A 113 LED5_0 102 LED5_1 103 TXRX5P_B 115 TXRX5M_B 116 TXRX5P_C 117 TXRX5M_C 118 TXRX5P_D 120 TXRX5M_D 121 TX_CLK6/REFCLKI6 48 TX_EN6/TX_CTL6 49 RX_CLK6/REFCLKO6 57 RX_DV6/CRS_DV6/RX_CTL6 58 TX_ER6 50 COL6 51 TXD6_3 52 TXD6_2 53 TXD6_1 54 TXD6_0 55 RX_ER6 59 CRS6 60 RXD6_3 62 RXD6_2 63 RXD6_1 64 RXD6_0 65 IBA 67 S_REFCLKP 73 S_REFCLKM 74 S_REXT 76 S_TX7M 78 S_TX7P 79 S_RX7M 82 S_RX7P 81 PME_N 93 GPIO_1 90 INTRP_N 94 SYNCLKO 95 RESET_N 96 SDO 97 SDI/SDA/MDIO 98 SCS_N 100 SCL/MDC 101 X0 125 XI 126 ISET 127 KSZ9477S U6A KSZ9477 Reset RGMII layout requirements 1. Match lengths within 50 to 100 mils. 2. RX signals do not need to be length matched to TX signals. 3. Due to RGMII timing error in port 6 of KSZ9477, plus SAMA5D36 compliance to RGMII v1.3, GTXCK must be routed for additional 2.0 ns delay relative to GTXD[3:0] and GTXCTL. 4.7k R103 GND 2 RESETn 1 WDI 4 RESET 3 VCC 6 MRn 5 MIC826TYMT ePAD 7 U14 10k R149 10k R150 10k R151 10k R152 TP5 191R 1% R98 PME_N 8 PME_N GRXCTL GRXCK Aardvark P6 100 Mbps Fast Link Mode LED2_0 AN / FL Speed LED4_0 LED1_0 Flow Ctrl LED1_1 Fast Link En LED2_1 Serial IF LED4_1 Start Switch LED5_1 IBA Enable 1 2 3 4 5 6 7 8 J16 10k R153 RST_PHY_N 8 MR_N 6 3V3 IBA_EN IBA_EN Install jumpers for CPU to control SPI. Remove jumpers in 4x2 header when connecting external SPI or I2C controller to the 5x2 header. |
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