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TMS320F2811PBKA 数据表(PDF) 13 Page - Texas Instruments

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部件名 TMS320F2811PBKA
功能描述  TMS320F281x Digital Signal Processors
PDF  175 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TMS320F2811PBKA 数据表(HTML) 13 Page - Texas Instruments

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Table 7-1. Signal Descriptions (continued)
NAME
PIN NO. (1)
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL
GHH/ZHH
176-PIN
PGF
128-PIN
PBK
JTAG
TRST
B12
135
98
I
PD
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system
control of the operations of the device. If this
signal is not connected or driven low, the
device operates in its functional mode, and the
test reset signals are ignored. NOTE: Do not
use pullup resistors on TRST; it has an internal
pulldown device. TRST is an active-high test
pin and must be maintained low at all times
during normal device operation. In a low-noise
environment, TRST may be left floating. In
other instances, an external pulldown resistor is
highly recommended. The value of this resistor
should be based on drive strength of the
debugger pods applicable to the design. A 2.2-
kΩ resistor generally offers adequate
protection. Since this is application-specific, it is
recommended that each target board be
validated for proper operation of the debugger
and the application.
TCK
A12
136
99
I
PU
JTAG test clock with internal pullup
TMS
D13
126
92
I
PU
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
TDI
C13
131
96
I
PU
JTAG test data input (TDI) with internal pullup.
TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDO
D12
127
93
O/Z
–
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge
of TCK.
EMU0
D11
137
100
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this
pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With
the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on
the TRST pin would latch the device into
boundary-scan mode. NOTE: An external
pullup resistor is recommended on this pin. The
value of this resistor should be based on the
drive strength of the debugger pods applicable
to the design. A 2.2-kΩ to 4.7-kΩ resistor is
generally adequate. Since this is application-
specific, it is recommended that each target
board be validated for proper operation of the
debugger and the application.
www.ti.com
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812
TMS320F2812-Q1



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