ADL9005ACPZN-R7 datasheet(23/24 Pages) AD

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Data Sheet

ADL9005

Rev. 0 | Page 23 of 24

PROVIDING DRAIN BIAS THROUGH THE

ACG4/VDD2 PIN

An alternative way to bias the ADL9005 is through the ACG4/VDD2

pin (Pin 24), which is shown in Figure 78. Because of the voltage

drop across the internal bias resistor, a higher VDD is required.

If a 300 Ω bias resistor (R1) is used and connected to the 5 V

power supply, which results in a total current of 80 mA, a VDD

of 8.5 V is recommended. R1 can also be connected to the VDD

of 8.5 V. In this case, to set IDQ to 80 mA, use an R1 value of

850 Ω on RBIAS. The performance of this circuit is summarized

in Figure 67 to Figure 72.

300Ω

100pF

CIN

0.1µF

RF INPUT

RFIN

RBIAS

0.01µF

RFOUT/VDD

4.7µF

C10

100pF

C11

0.01µF

4.7µF

COUT

0.1µF

OUTPUT

VDD

(8.5V)

ADL9005

Figure 78. Providing Resistive Drain Bias Through the ACG4/VDD2 Pin

POWER-UP AND POWER-DOWN SEQUENCING

Apply the RF input signal after the main supply voltage and

the voltage driving RBIAS (R1 in Figure 74 and Figure 78) and

remove the RF input signal before the main supply voltage and

the voltage on RBIAS are turned off. The voltage on RBIAS can either

be applied simultaneously with VDD or after VDD is applied.

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