6.4

CTRL (04h) - RW

7

6

5

4

3

2

1

0

LOW_ODR

START

BDU

AVG1

AVG0

IF_ADD_INC

FREERUN

TIME_OUT_

DIS

ONE_SHOT

LOW_ODR_START

Enables 1 Hz ODR operating mode.

This bit must be set to ‘1’ only when the LOW_ODR_ENABLE bit in SOFTWARE_RESET (0Ch) - RW is

set to '1' (refer to Section 9.3 Enable sequence for low-ODR mode).

BDU

Default is set to 0 for BDU disabled; 1 for BDU enabled (if BDU is used, TEMP_L_OUT must be read

first).

AVG[1:0]

These bits are used to set the number of averages configuration. When in freerun mode, these bits also

set the ODR (see Table 13. Average configuration).

IF_ADD_INC

If this bit is set to '1', the automatic address increment is enabled when multiple I²C read and write

transactions are used.

FREERUN

Enables freerun mode (see Section 9.2 Enable sequence for freerun mode).

TIME_OUT_DIS

If this bit is set to ‘1’, the timeout function of SMBus is disabled.

ONE_SHOT

If this bit is set to 1, a new one-shot temperature acquisition is executed (see Section 9.1 Enable

sequence for one-shot mode).

AVG

# means

ODR when in freerun

0

8

25 Hz

1

4

50 Hz

2

2

100 Hz

3

1

200 Hz

6.5

STATUS (05h) - RO

7

6

5

4

3

2

1

0

0

0

0

0

0

UNDER_THL

OVER_THH

BUSY

UNDER_THL

0: Low limit temperature not exceeded (or disabled).

1: Low limit temperature exceeded.

The bit is automatically reset to ‘0’ upon reading the STATUS register.

OVER_THH

0: High limit temperature not exceeded (or disabled).

1: High limit temperature exceeded. The bit is automatically reset to ‘0’ upon reading the STATUS register.

BUSY

The BUSY bit is applicable to one-shot mode only :

0: The conversion is complete.

1: The conversion is in progress.

STTS22H

CTRL (04h) - RW

DS12606 - Rev 4

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