LTC7802EUFDM-3.3 datasheet(21/34 Pages) AD

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LTC7802-3.3

Rev. 0

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current pulses required through the input capacitor’s

ESR. This is why the input capacitor’s requirement cal-

culated above for the worst-case controller is adequate

for the dual controller design. Also, the input protection

fuse resistance, battery resistance, and PC board trace

resistance losses are also reduced due to the reduced

peak currents in a 2-phase system. The overall benefit of

a multiphase design will only be fully realized when the

source impedance of the power supply/battery is included

in the efficiency testing.

The drains of the top MOSFETs should be placed within

1cm of each other and share a common CIN(s). Separating

the drains and CIN may produce undesirable resonances

at VIN.

A small (0.1μF to 1μF) bypass capacitor between the chip

VIN pin and ground, placed close to the LTC7802-3.3, is

also suggested. An optional 1Ω to 10Ω resistor placed

between CIN and the VIN pin provides further isolation

from a noisy input supply.

The selection of COUT is driven by the effective series

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

output ripple (ΔVOUT) is approximated by:

ΔVOUT ≈ ΔIL ESR +

8fCOUT

⎛

⎝

⎜

⎞

⎠

⎟

where f is the operating frequency, COUT is the output

capacitance and ΔIL is the ripple current in the inductor.

The output ripple is highest at maximum input voltage

since ΔIL increases with input voltage.

Setting the Output Voltage

For channel 1, directly connect the LTC7802-3.3’s VOUT1

pin to the output to regulate the output voltage to 3.3V.

For channel 2, the output voltage is set by an external

feedback resistor divider carefully placed across the out-

put, as shown in Figure 4. The regulated output voltage

is determined by:

VOUT2 = 0.8V 1+

⎛

⎝

⎜

⎞

⎠

⎟

APPLICATIONS INFORMATION

Figure 4. Setting Channel 2 Output Voltage

780233 F04

LTC7802-3.3

VFB2

CFF

VOUT

Place resistors RA and RB very close to the VFB2 pin to

minimize PCB trace length and noise on the sensitive VFB2

node. Great care should be taken to route the VFB2 trace

away from noise sources, such as the inductor or the

SW trace. To improve frequency response, a feedforward

capacitor (CFF) may be used.

RUN Pins and Undervoltage Lockout

The two channels of the LTC7802-3.3 are enabled using

the RUN1, and RUN2 pins. The RUN pins have a rising

threshold of 1.2V with 100mV of hysteresis. Pulling a

RUN pin below 1.1V shuts down the main control loop

and resets the soft-start for that channel. Pulling both

RUN pins below 0.7V disables the controllers and most

internal circuits, including the INTVCC LDOs. In this state,

the LTC7802-3.3 draws only ≈1.5μA of quiescent current.

The RUN pins are high impedance and must be externally

pulled up/down or driven directly by logic. Each RUN pin

can tolerate up to 40V (absolute maximum), so it can be

conveniently tied to VIN in always-on applications where

the controller is enabled continuously and never shut

down. Do not float the RUN pins.

The RUN pins can also be configured as precise under-

voltage lockouts (UVLOs) on the input supply with a resis-

tor divider from VIN to ground, as shown in Figure 5.

The VIN UVLO thresholds can be computed as:

UVLO RISING = 1.2V 1+

⎛

⎝

⎜

⎞

⎠

⎟

UVLO FALLING = 1.1V 1+

⎛

⎝

⎜

⎞

⎠

⎟

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