9DB306BL

www.icst.com/products/hiperclocks.html

REV. A APRIL 7, 2005

7

Integrated

Circuit

Systems, Inc.

ICS9DB306

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin.The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

and R2/R1 = 0.609.

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. The ICS9DB306 provides separate

power supplies to isolate any high switching noise from the out-

puts to the internal PLL. V

nected to the power supply plane through vias, and bypass ca-

pacitors should be used for each pin. To achieve optimum jitter

performance, power supply isolation is required.

Figure 1 illus-

trates how a 24

Ω resistor along with a 10μF and a .01μF by-

pass capacitor should be connected to each V

24

Ω

V

CCA

10

μF

.01

μF

3.3V

.01

μF

V

CC

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLKx

nCLKx

VCC