2

ICS952301

Advance Information

0673—07/09/02

Pin Descriptions

PIN # PIN

PIN

TYPE

DESCRIPTION

1

GNDREF

PWR

Ground pin.

2

X1

IN

Crystal input, nominally 14.318MHz.

3

X2

OUT

Crystal output, nominally 14.318MHz.

4PD#

IN

Asynchronous active low input pin used to power down the

device into a low power state. The internal clocks are

disabled and the VCO and the crystal are stopped. The

latency of the power down will not be greater than 3ms.

5

PCICLK0

OUT

PCI clock outputs.

6

PCICLK1

OUT

PCI clock outputs.

7

GNDPCI

PWR

Ground pin.

8

VDDPCI

PWR

Supply for PCI, nominal 3.3V.

9

PCICLK21

OUT

PCI clock outputs.

10

PCICLK3

OUT

PCI clock outputs.

11

PCICLK41

OUT

PCI clock outputs.

12

GNDPCI

PWR

Ground pin.

13

VDDPCI

PWR

Supply for PCI, nominal 3.3V.

14

PCICLK5

OUT

PCI clock outputs.

15

PCICLK6

OUT

PCI clock outputs.

16

SDATA

I/O

Data pin for I

17

24-48MHz/Sel

48_24#*

I/O

Selectable 48 or 24MHz output

18

48MHz

OUT

48MHz output clock

19

GND48

PWR

Ground pin.

20

VDD48

PWR

Power for 24 & 48MHz output buffers and fixed PLL core.

21

SCLK

IN

Clock pin of I

22

PCI_STOP#

IN

Stops all PCICLKs besides the PCICLK_F clocks at logic 0

level, when input low

23

CPUCLK0

OUT

CPU clock outputs.

24

GNDCPU/CORE

PWR

Ground pin.

25

VDDCPU/CORE

PWR

3.3V power for the PLL core.

26

CPU_STOP#

IN

Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0

level, when input low

27

REF/ 1X or 2X

Programmable*

OUT

14.318 MHz reference clock. Latched input select for strength

of PCICLK(4,2). Default 1X with internal pullup.

28

VDDREF

PWR

3.3V power for the REF.