CO

NFI

DE

NTI

AL

III.5.8 - PWM and Counter Module

This unit includes three separate pulse width

modulator (PWM) generators using a shared

counter, and three timer compare and capture

channels sharing a second counter.

The counters can be clocked from a pre-scaled

internal clock or from a pre-scaled external clock

via the capture clock input and the event on which

the timer value is captured is also programmable.

The PWM counters are 8-bit with 8-bit registers to set

the output high time. The capture/compare counter

and the compare and capture registers are 32-bit.

III.5.9 - Parallel Programmable IO Module

Forty bits of parallel IO are provided. Each bit is

programmable as an output or an input. The output

can be configured as a totem pole or open drain

driver. Input compare logic is provided which can

generate an interrupt on any change on any input bit.

Many pins of the STi5500 device are multi-function

and can either be configured as PIO or connected

to an internal peripheral signal.

III.5.10 - MPEG Video Decoder

The video decoder is a real-time video compression

processor supporting the MPEG-1 and MPEG-2

standards at video rates up to 720 x 480 x 60 Hz and

720 x 576 x 50Hz. Picture format conversionfor display

is performed by vertical and horizontal filters. User-de-

fined bitmaps may be superimposed on the display

picture through use of the on-screen display function.

III.5.11 - PAL/NTSC encoder

The digital encoder which is integrated in the STi5500

produces, from a multiplexed 4:2:2 YUV stream

simultainious RGB,CVBS and component outputs

on two triple DACs. The encoder can also perform

cloased-caption, CGMS or teletext encoding and

allows MacrovisionTM 7.01/6.1 copy protection.

III.5.12 - MPEG-1 Audio Decoder

The audio decoder is a fully compliant MPEG-1

decoder (Layers 1 & 2)

III.6 - STi 5500 Internal Architecture and Dataflow

Reference is made to the STi5500 internal archi-

tecture block diagram, figure 2 in this section.

The intention of the OMEGA architecture is to allow

as much flexibility as possible for a user to design

a memory system and arrange data in a manner

which best fits the system needs. There are two

main memory systems.

One dedicated to the ST20 called the ST20 EMI,

this interface can support directly SRAM, DRAM,

ROM and FLASH and a second interface which is

used by the MPEG decoders (audio and video) and

supports only SDRAM. An important architectural

feature of the device is that the SDRAM memory

can be viewed by the ST20 as an extension of it’s

own memory system. The ST20 memory arbitor

can make requests into the SDRAM arbitor which

are treated as the highest priority. A mechanism is

implemented to ensure that the microprocessor

cannot block out completely the MPEG decoder

form the SDRAM.

The STi 5500 device is divided into essentially two

main parts. The CPU system and peripherals and

the MPEG video/audio decoder system. The whole

system is built around four interconnected arbitors.

- The CPU arbitor,

- The Comunications (DMA) arbitor),

- The ST20 arbitor,

- The SDRAM arbitor.

Starting at the lowest level the CPU arbitor sched-

ules outgoing requests to the memory system com-

ing from the cache refil controller with the incoming

requests from the ST20 arbitor to the internal

SRAM.

The communications arbitor schedules all the re-

quests for access to the ST20 arbitor and conse-

quently the memory system coming from the DMA

engines. The CPU and the communications arbi-

tors consequently make requests into the the ST20

arbitor and are scheduled along with the requests

from the front-end interface in the following priority :

- Link Interface - Highest priority,

- CPU arbitor - round robin with communications

arbitor,

- Communications arbitor - round robin with CPU

arbitor,

There are four possible destinations for these three

requestors :

- Shared Memory Interface (SDRAM),

- Compressed data port,

- Register port ( for audio, video and DENC blocks),

- ST20 external memory interface.

The ST20 arbitor works like a bus in that only one

access can be on-going at any one time, however

a split-transaction scheme allows tasks to be

queued at the receivers and allows the requesters

to have multiple outstanding requests.

This means a transaction does not have to be

complete for another transaction to take place over

the arbitor. Hence, slow interfaces or transactions

do not slow down the internal communications.

III - INTERNAL CIRCUIT DESCRIPTION (continued)

STi5500

9/11