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LM4846TL 数据表(PDF) 13 Page - National Semiconductor (TI) |
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LM4846TL 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 19 page ![]() Application Information (Continued) NATIONAL 3D ENHANCEMENT The LM4846 features a stereo headphone, 3D audio en- hancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo head- phone listening. The LM4846 can be programmed for a “narrow” or “wide” soundstage perception. The narrow soundstage has a more focused approaching sound direc- tion, while the wide soundstage has a spatial, theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed: low, medium, high, and maximum (Table 2), each level with an ever increasing aural effect, respectively. The difference between each level is 3dB. The external capacitors, shown in Figure 6, are required to enable the 3D effect. The value of the capacitors set the cutoff frequency of the 3D effect, as shown by Equations 1 and 2. Note that the internal 20k Ω resistor is nominal (±25%). f 3DL(-3dB) =1/2 π * 20kΩ *C 3DL (1) f 3DR(-3dB) =1/2 π * 20kΩ *C 3DR (2) Optional resistors R 3DL and R3DR can also be added (Figure 7) to affect the -3dB frequency and 3D magnitude. f 3DL(-3dB) =1/2 π * (20kΩ +R 3DL)*C3DL (3) f 3DR(-3dB) =1/2 π * 20kΩ +R 3DR)*C3DR (4) ∆AV (change in AC gain)=1/1+M, where M represents some ratio of the nominal internal resistor, 20k Ω (see ex- ample below). f 3dB (3D)=1/2 π (1 + M)(20kΩ *C 3D) (5) C Equivalent (new) = C3D /1+M (6) TABLE 6. Pole Locations R 3D (k Ω) (optional) C 3D (nF) M ∆AV (dB) f-3dB (3D) (Hz) Value of C 3D to keep same pole location (nF) new Pole Location (Hz) 068 0 0 117 1 68 0.05 –0.4 111 64.8 117 5 68 0.25 –1.9 94 54.4 117 10 68 0.50 –3.5 78 45.3 117 20 68 1.00 –6.0 59 34.0 117 PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8 Ω LOAD Power dissipated by a load is a function of the voltage swing across the load and the load’s impedance. As load imped- ance decreases, load dissipation becomes increasingly de- pendent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load’s connec- tions. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 Ω trace resistance reduces the output power dissipated by an 8 Ω load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output volt- age swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply’s output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, 20166895 FIGURE 6. External 3D Effect Capacitors 20166894 FIGURE 7. External RC Network with Optional R 3DL and R 3DR Resistors www.national.com 13 |
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