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AM79C02JC 数据表(PDF) 28 Page - Advanced Micro Devices |
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AM79C02JC 数据表(HTML) 28 Page - Advanced Micro Devices |
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28 / 48 page ![]() 28 Am79C02/03/031(A) Data Sheet 6. MCLK Selection (10h/12h) MCLK may be selected to operate from a 2.048 MHz or 4.096 MHz external clock. MCLK selection on either channel affects both channels. A = 0: 2.048 MHz A = 1: 4.096 MHz 7. Write Transmit Time Slot and PCM Highway Selection (40h) PCM = 0: Highway A PCM = 1: Highway B TS: Time slot number 0 to 127 The PCM Highway B is not available on the Am79C031(A). The Transmit section of both channels must not be set to the same time slot on the same output port simultaneously. 8. Read Transmit Time Slot and PCM Highway Selection (41h) 9. Write Receive Time Slot and PCM Highway Selection (42h) PCM = 0: Highway A PCM = 1: Highway B TS: Time slot number 0 to 127 The PCM Highway B is not available on the Am79C031(A). 10. Read Receive Time Slot and PCM Highway Selection (43h) D7 D6 D5 D4 D3 D2 D1 D0 Command 0 0 0 1 0 0 A 0 D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 0 0 0 0 0 Output Data PCM TS TS TS TS TS TS TS D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 0 0 0 0 1 Output Data PCM TS TS TS TS TS TS TS D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 0 0 0 1 0 Output Data PCM TS TS TS TS TS TS TS D7 D6 D5 D4 D3 D2 D1 D0 Command 0 1 0 0 0 0 1 1 Output Data PCM TS TS TS TS TS TS TS |
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