MODEL: AD3V

AD3V SPECIFICATIONS

ES-1389 Rev.24 Page 2/9

https://www.m-system.co.jp/

• Data output logic

• HOLD input logic

• DAV output logic

• DAV output time

• Output rate ‘n’ ratio

• Parity check

• etc.

For detailed information, refer to the instruction manual.

■DISPLAY

LED: 7 mm (.28") 7 segment, red

Number of display digits: 4 digits for DATA display; 2 digits

for ITEM display

PV indication: Output signal in engineering unit

Overrange indication: LEDs blinking

Power saving mode: Displays turn off if the keys are

untouched for a preset time period

PL1 (POL) LED: Red LED turns on at negative polarity.

PL2 (HOLD) LED: Red LED turns on at HOLD.

INPUT SPECIFICATIONS

■ DC Current: 0 – 50 mA DC; shunt resistor attached to

input terminals (0.5 W)

Operational range: 0 – 70 mA DC (with 100 Ω/0.5 W)

Usable range:

• Max. range: 0 - 50 mA DC

• Min. step: 0.1 mA DC

• Input setting must: 100 % setting ≥ 0 % setting

• Input value is operational range or 15 to +115 %.

■ DC Voltage

Operation range:

S1: -1.15 to +1.15 V DC

S2: -11.5 to +11.5 V DC

S3: -34.5 to +34.5 V DC

Usable range:

• Max. range:

S1: -1 to +1 V DC

S2: -10 to +10 V DC

S3: -30 to +30 V DC

• Min. step:

S1: 10m V DC

S2: 100m V DC

S3: 100m V DC

• Input setting must: 100 % setting ≥ 0 % setting

• Input value is operational range or 15 to +115 %.

■ Hold Input: TTL level (5 V - CMOS level)

Commands to stop data renewal;

Choose from below:

Hold with low or short

Hold with high or open

(detecting voltage: approx. 5 V, saturation voltage: ≤ 1 V,

sink current: 0.5 mA)

OUTPUT SPECIFICATIONS

■ Output Code: Code, logic and scaling are user-selectable.

BCD with polarity (Settable range: -9999 - 9999)

Binary with polarity (Settable range: -7FFF - 7FFF)

Offset binary (Settable range: 0000 - FFFF)

Two’s complement (Settable range: 8000 - 7FFF)

Reflected binary (Settable range: 0000 - FFFF)

Output code, logic, scaling are settable.

■ Available number of bits

Selectable from 8, 10, 12, 14, 16 bits

■ Output Level

• Open Collector

Max. collector-emitter voltage: 30 V DC

Max. collector current: 30 mA

Saturation voltage:

NPN ≤ 1.1 V negative common

PNP ≤ 2.0 V positive common

• CMOS Level

H output: ≥ 4.5 V DC

L output: ≤ 0.5 V DC

Common: Negative

■ POL output (Polarity): Same logic and level as for the

output code; logic user-selectable

■ OVF output (Overflow): Same logic and level as for the

output code; logic user-selectable

■ DAV output (Data available): Same level as for the output

code; logic user-selectable

■ Odd or even parity: Same level as for the output code;

logic user-selectable

INSTALLATION

Power consumption

•AC: Approx. 10 VA

•DC: Approx. 4 W (160 mA at 24 V)

Operating temperature: -5 to +55°C (23 to 131°F)

Operating humidity: 30 to 90 %RH (non-condensing)

Mounting: Surface or DIN rail

Weight: 260 g (0.57 lb)

PERFORMANCE in percentage of max. span

Accuracy: ±0.1 %

Min. span required to ensure the accuracy: 20 % of the

nominal output range

Temp. coefficient: ±0.015 %/°C (±0.008 %/°F)

Resolution: 16 bits

Response time: 0.15 – 60 sec. (0 – 90 %) programmable at

front key pad.

Line voltage effect: ±0.1 % over voltage range

Insulation resistance: ≥ 100 MΩ with 500 V DC

Dielectric strength: 2000 V AC @1 minute (input to output

to power to ground)