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DSC8123AI1-T 数据表(PDF) 2 Page - Micrel Semiconductor

部件名 DSC8123AI1-T
功能描述  Programmable Low-Jitter Precision LVDS Oscillator
PDF  6 Pages
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制造商  MICREL [Micrel Semiconductor]
网页  http://www.micrel.com
标志 MICREL - Micrel Semiconductor

DSC8123AI1-T 数据表(HTML) 2 Page - Micrel Semiconductor

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All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Micrel, Inc. Micrel Inc. may update or make changes
to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not limited to
implied warranties of merchantability or fitness for a particular use.
Page 2 |
MK-Q-B-P-D-110410-03-2
DSC8103
Programmable Low-Jitter Precision LVDS Oscillator
DSC8123
Absolute Maximum Ratings
Item
Min
Max
Unit
Condition
Supply Voltage
-0.3
+4.0
V
Input Voltage
-0.3
VDD+0.3
V
Junction Temp
-
+150
°C
Storage Temp
-55
+150
°C
Soldering Temp
-
+260
°C
40sec max.
ESD
HBM
MM
CDM
-
4000
400
1500
V
Ordering Code
Note: 1000+ years of data retention on internal memory
Specifications
Notes:
1.
Pin 6 VDD should be filtered with 0.1uf capacitor.
2.
tsu is time to 100ppm of output frequency after VDD is applied and outputs are enabled.
3.
Output Waveform and Test Circuit figures below define the parameters.
4.
Output is enabled if pad is floated or not connected.
Parameter
Condition
Min.
Typ.
Max.
Unit
Supply Voltage1
VDD
2.25
3.6
V
Supply Current
IDD
EN pin low – outputs are disabled
DSC8103
DSC8123
20
0.095
22
mA
Frequency Stability
Δf
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
±10
±25
±50
ppm
Aging
Δf
1 year @25°C
±5
ppm
Startup Time2
tSU
T=25°C
5
ms
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
0.25xVDD
V
Output Disable Time3
tDA
5
ns
Output Enable Time
tEN
DSC8103
DSC8123
5
20
ms
ns
Enable Pull-Up Resistor4
Pull-up resistor exist
40
LVDS Outputs
Supply Current
IDD
Output Enabled, RL=50Ω
29
32
mA
Output offset Voltage
VOS
R=100Ω Differential
1.125
1.4
V
Delta Offset Voltage
∆VOS
50
mV
Pk to Pk Output Swing
VPP
Single-Ended
350
mV
Output Transition time3
Rise Time
Fall Time
tR
tF
20% to 80%
RL=50Ω, CL= 2pF
200
ps
Frequency
f0
Single Frequency
10
460
MHz
Output Duty Cycle
SYM
Differential
48
52
%
Period Jitter
JPER
2.5
psRMS
Integrated Phase Noise
JPH
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
2
psRMS
DSC81 0
Enable Modes
0: Enable/Standby
2: Enable/Disable
-
Packing
T: Tape & Reel
: Tube
3 C I 5
Package
A: 7.0x5.0mm
B: 5.0x3.2mm
C: 3.2x2.5mm
D: 2.5x2.0mm
Temp Range
E: -20 to 70
I: -40 to 85
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
T



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