PL123-05/-09

Low Skew Zero Delay Buffer

Page 2

PIN DESCRIPTIONS

Name

PL123-09

PL123-05

Type

Description

TSSOP-16L

SOP-16L

SOP-8L

1

1

1

I

Input reference frequency.

2

2

3

O

Buffered clock output, Bank A

3

3

2

O

Buffered clock output, Bank A

VDD

4,13

4,13

6

P

VDD connection

GND

5,12

5,12

4

P

GND connection

6

6

-

O

Buffered clock output, Bank B

7

7

-

O

Buffered clock output, Bank B

8

8

-

I

Selector input

9

9

-

I

Selector input

10

10

-

O

Buffered clock output, Bank B

11

11

-

O

Buffered clock output, Bank B

14

14

5

O

Buffered clock output, Bank A

15

15

7

O

Buffered clock output, Bank A

16

16

8

O

Buffered clock output. Internal feedback

on this pin.

Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2

SELECTOR DEFINITION FOR PL123-09

S2

S1

CLOCK A1–A4

(Bank A)

CLOCK B1–B4

(Bank B)

CLKOUT

Output Source

PLL Shutdown

0

0

Three-state

Three-state

Driven

PLL

N

0

1

Driven

Three-state

Driven

PLL

N

1

0

Driven

Driven

Driven

Reference

Y

1

1

Driven

Driven

Driven

PLL

N

INPUT / OUTPUT SKEW CONTROL

The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-

ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.

Please contact Micrel for more information.