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ATSAM3308

6090A–DRMSD–08/04

Recommended Board

Layout

Like all HCMOS high integration ICs, following simple rules of board layout is mandatory

for reliable operations:

•

GND, VC33, VC18 distribution, decoupling

All GND, VC33, VC18 pins should be connected. A GND plane is strongly recom-

mended. The board GND + VC33 distribution should be in grid form.

Recommended VC18 decoupling is 0.1 µF at each corner of the IC with an additional 10

µF decoupling close to the crystal. VC33 requires a single 0.1 µF decoupling.

•

Crystal, LFT

The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-

R and the IC should be short and shielded. The ground return from the compensation

capacitors and LFT filter should be the GND plane from the IC.

•

Buses

Parallel layout from D0 - D7 and WA0 - WA21/WD0 - WD15 should be avoided. The D0

- D7 bus is an asynchronous type bus. Even on short distances, it can induce pulses on

WA0 - WA21/WD0 - WD15 which can corrupt address and/or data on these buses.

A ground plane should be implemented below the D0 - D7 bus that connects both to the

host and to the IC GND.

A ground plane should be implemented below the WA0 - WA21/WD0 - WD15 bus that

connects both to the ROM/Flash grounds and to the IC.

•

Analog Section

A specific AGND ground plane should be provided, which connects by a single trace to

the GND ground. No digital signals should cross the AGND plane. Refer to the Codec

vendor recommended layout for correct implementation of the analog section.