HT83XXX

Rev. 0.10

14

August 25, 2003

Preliminary

The WDT overflow under normal operation will initialize

a

²chip reset² and set the status bit ²TO². Whereas in

the HALT mode, the overflow will initialize a

²warm re -

set

² only the PC and SP are reset to zero. To clear the

contents of the WDT (including the WDT prescaler),

three methods are adopted; external reset (external re-

set (a low level to RES), software instructions, or a

HALT instruction. The software instruction is

²CLR

WDT

² and execution of the ²CLR WDT² instruction will

clear the WDT.

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

M a s k

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

WS7

WS6

WS5

WS4

WS3

WS2

WS1

WS0

Division Ratio

¾¾¾¾¾

000

1:1

¾¾¾¾¾

001

1:2

¾¾¾¾¾

010

1:4

¾¾¾¾¾

011

1:8

¾¾¾¾¾

1

0

0

1:16

¾¾¾¾¾

1

0

1

1:32

¾¾¾¾¾

1

1

0

1:64

¾¾¾¾¾

1

1

1

1:128

WDTS Register

Power Down

- HALT

The HALT mode is initialized by a HALT instruction and

results in the following:

oscillator keeps running (if the WDT oscillator is se-

lected).

unchanged.

again.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a

²warm reset². By examining the TO and PDF

flags, the reason for the chip reset can be determined.

The PDF flag is cleared when the system powers-up or

executes the

²CLR WDT² instruction, and is set when

the

²HALT² instruction is executed. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only

resets the PC and SP. The other maintain their original

status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by mask option. Awakening from an I/O port

stimulus, the program will resume execution of the next

instruction. If awakening from an interrupt, two se-

quence may occur. If the related interrupt is disabled or

the interrupt is enabled by the stack is full, the program

will resume execution at the next instruction. If the inter-

rupt is enabled and the stack is not full, the regular inter-

rupt response takes place.

Once a wake-up event occurs, it takes 1024 system

clock period to resume normal operation. In other

words, a dummy cycle period will be inserted after a

wake-up. If the wake-up results from an interrupt ac-

knowledge, the actual interrupt subroutine will be de-

layed by one more cycle. If the wake-up results in next

instruction execution, this will be executed immediately

after a dummy period is finished. If an interrupt request

flag is set to

²1² before entering the HALT mode, the

wake-up function of the related interrupt will be dis-

abled. To minimize power consumption, all I/O pins

should be carefully managed before entering the HALT

status.