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AX88850 数据表(PDF) 21 Page - ASIX Electronics Corporation

部件名 AX88850
功能描述  100BASE-TX/FX Repeater Controller
PDF  39 Pages
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制造商  ASIX [ASIX Electronics Corporation]
网页  http://www.asix.com.tw
标志 ASIX - ASIX Electronics Corporation

AX88850 数据表(HTML) 21 Page - ASIX Electronics Corporation

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AX88850
PRELIMINARY
ASIX ELECTRONICS CORPORATION
21
3.6 Expansion Logic(Cascade Interface)
The expansion logic is used to stack numerous repeaters. The expansion logic can be divided into two types:
Expansion Logic with Buffer (maximum mode
In this mode, use /IR_ACTO[7:0] and /IR_ACTI[7:0] to cascade repeaters. Buffers are used both in
/IR_ACTO[7:0] and /IR_ACTI[7:0]. This mode is supposed to cascade repeaters on difference boards via cables.
There is a configuration bit /IR_ACT_EN to decide cascade signals are judges by /IR_ACTI[7:0](/IR_ACT_EN
= 0) or /IR_ACTO[7:0](/IR_ACT_EN = 1).
Expansion Logic without Buffer (minimum mode)
In this mode, use /IR_ACTO[7:0] to cascade repeaters. Just connect /IR_ACTO[7:0] without using buffer in this
part. This mode is supposed to cascade repeaters on the same board.
/IR_ACTO<7:0>
RPTR_ID<2:0>
Idle
Active
Collision
0
FFh
FEh
FBh
1
FFh
FDh
FCh
2
FFh
FBh
F9h
3
FFh
F7h
F3h
4
FFh
EFh
E7h
5
FFh
DFh
CFh
6
FFh
BFh
9Fh
7
FFh
7Fh
3Fh
In this table:
a.
All /IR_ACTO[7:0] will be in open-drain state when repeater chip is idle. These signals are all high via
external pull high resister.
b.
One signal of /IR_ACTO[7:0] is low in data forwarding state corresponding to different RPTR_ID[2:0].
c.
Two signals of /IR_ACTO[7:0] are low in collision state corresponding to different RPTR_ID[2:0].
3.7 Management Logic
AX88850 provides the required management information associated with a packet for management chip which
statistics processed on a per packet basis. Transmit ready signal TX_RDY is used as a framing signal for management
data MD. Then management chip uses this data to determine the source of the current packet. MD data is synchronized
to the rising edge of IRD_CK. When collision occur, MD will be tri-state and becomes invalid.
MD frame format
idle
start bit
data0
data1
data2
data3
data4
data5
data6
1
0
PID[0]
PID[1]
PID[2]
PID[3]
PID[4]
RID_CH
PARITY
Notes:
a.
PID[4:0] is the number of the receiving port.
b.
RID_CH indicates change in RID.
c.
PARITY = 1 when sum of 1‘s among PID[4:0] and RID_CH is even
PARITY = xnor (PID[4],PID[3],PID[2],PID[1],PID[0],RID_CH)



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