AX88852 datasheet(13/39 Pages) ASIX

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AX88850

PRELIMINARY

ASIX ELECTRONICS CORPORATION

2.1B MII interface (share bus MII group 0 port & MII group 1 port)

M0 -- MII group 0 ; M1 -- MII group 1

Signal Name

Type Pin No.

Description

M0_TX_ER

M1_TX_ER

O/ML

Transmit Error : TX_ER is transition synchronously with respect to the rising

edge of TX_CLK . Asserted high when a code violation is request to be send

M0_TXD[3:0]

M1_TXD[3:0]

O/H

21-18

37-34

Transmit Data : TXD[3:0] is transition synchronously with respect to the

rising edge of TX_CLK. For each TX_CLK period in which TX_EN is

asserted, TXD[3:0] are accepted for transmission by the PHY.

M0_TX_EN[7:0]

M1_TX_EN[7:0]

O/L

4,3,203,

202,

189-186

74,65-63,

50-47

Transmit Enable : TX_EN is transition synchronously with respect to the

rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles

on TXD [3:0] for transmission.

M0_RXD[3:0]

M1_RXD[3:0]

I/PU

13-10

29,26-24

Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to

RX_CLK.

M0_RX_ER

M1_RX_ER

I/PD

Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is

asserted for one or more RX_CLK periods to indicate to the port that an error

has detected.

M0_RX_CLK

M1_RX_CLK

Receive Clock : RX_CLK is a continuous clock that provides the timing

reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from

the PHY to the MII port of the repeater.

M0_RX_DV

M1_RX_DV

I/PD

Receive Data Valid : RX_DV is driven by the PHY synchronously with

respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].

M0_CRS[7:0]

M1_CRS[7:0]

I/PD

207-204,

194-191

56-53,

43-40

Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either

the transmit or receive medium is non-idle.

M0_RX_EN[7:0]

M1_RX_EN[7:0]

O/L

8-4,

201-199,

190

78-75,

62,61,59,

Receive Enable : Assert high to the respective PHY chip to enable its receive

data.

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