 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
UCD3138064RMHT 数据表(PDF) 20 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
UCD3138064RMHT 数据表(HTML) 20 Page - Texas Instruments |
|
|
20 / 104 page  8.9 Typical Clock Gating Power Savings 0.00 1.00 2.00 3.00 4.00 5.00 6.00 DPWM ADC12 Front-end Control Peak Current Mode Timer Filter Constant Power/Constant Current SCI GIO Module C001 Figure 8-4. Clock Gating Power Savings The power disable control register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more. By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved. UCD3138064 SLUSB72D – MARCH 2013 – REVISED APRIL 2021 www.ti.com 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: UCD3138064 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
