ADRF5044

Data Sheet

Rev. A | Page 6 of 14

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

GND

RFC

GND

GND

GND

V2

V1

VDD

GND

VSS

GND

1

2

3

4

5

6

7

8

9

101112

13

14

15

16

17

18

19

20

21

22

23

24

ADRF5044

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PAD MUST BE

CONNECTED TO THE RF/DC GROUND

OF THE PCB.

Figure 4. Pin Configuration (Top View)

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 4 to 7, 9, 10, 12,

13, 18, 19, 21, 22, 24

GND

Ground. These pins must be connected to the RF/dc ground of the PCB.

3

RFC

RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF

line potential is not equal to 0 V dc. See Figure 5 for the interface schematic.

8

RF4

RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line

potential is not equal to 0 V dc. See Figure 5 for the interface schematic.

11

RF3

RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line

potential is not equal to 0 V dc. See Figure 5 for the interface schematic.

14

VSS

Negative Supply Voltage.

15

V2

Control Input 2. See Table 5 for the control voltage truth table.

16

V1

Control Input 1. See Table 5 for the control voltage truth table.

17

VDD

Positive Supply Voltage.

20

RF2

RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line

potential is not equal to 0 V dc. See Figure 5 for the interface schematic.

23

RF1

RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF line

potential is not equal to 0 V dc. See Figure 5 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.

INTERFACE SCHEMATICS

RFC,

RF1,

RF2,

RF3,

RF4

Figure 5. RFx Pins (RFC and RF1 to RF4) Interface Schematic

V1, V2

Figure 6. Digital Pins (V1 and V2) Interface Schematic